1. Field of the Invention
The present invention relates to a network system for data transmission wherein a plurality of stations, i.e., transmitters or receivers are connected via a data transmission bus line and a separate synchronous signal transmission bus line and a predetermined code string signal is supplied to each station so that a plurality of addresses changing sequentially at a predetermined frequency are allocated among the stations.
2. Description of the Prior Art
Japanese Patent Publication No. 52-13367 and corresponding U.S. Pat. No. 3,757,050 published on Sept. 4, 1973, to Masanori Mizote discloses a multichannel transmission system for producing, transmitting and receiving pulse signals assigned to corresponding signal channels and modulated for information conveyance, the disclosure of which is incorporated by reference.
FIG. 1 shows a block diagram of a conventional data transmission network system exemplified in the above-described U.S. Pat. No. 3,757,050. In FIG. 1, a plurality of pairs of transmission stations (or transmitters) 4 and reception stations (or receivers) 5 are connected via a synchronous signal transmission bus line 2 and a data transmission bus line 3. The synchronous signal transmission bus line 2 provides a means for conducting the synchronous signal shown in FIG. 2(c) from a synchronous signal generator 1 to each station. The synchronous signal generator 1 generates a clock pulse train having a constant period .tau. as shown in FIG. 2(a), an M-sequence code string repeating the order of H(1), H(1), H(1), L(0), L(0), H(1), L(0) at a constant period (T) as shown in (b) of FIG. 2, a pulsewidth-modulated signal as shown in (c) of FIG. 2.
Each transmission station 4 comprises: (a) a receiver circuit 6 which receives the above-described synchronous signal and demodulates the clock pulse train and M-sequence signal shown in FIG. 2; (b) shift registers 7, 8, and 9 which shift sequentially the bits of the demodulated M-sequence signal in synchronization with the clock pulses; and (c) a logic circuit 10 which opens a gate circuit 11 when a predetermined logical value results from a logical operation on the outputs of the shift registers 7, 8, and 9.
FIG. 3 shows a combination pattern of the logical outputs D.sub.1, D.sub.2, and D.sub.3 of the shift registers 7, 8, and 9 in connection with the output X of the logic circuit 10 for each clock pulse of the clock pulse train signal. As seen from FIG. 3, seven different combinations of the levels "L" and "H" of the shift registers 7, 8, and 9 occur during the frequency period T of the above-described M-sequence signal.
Accordingly, if one of the seven combinations satisfies the logical condition of the logic circuit 10 in each transmission station 4 (for example, H, H, and L as shown in FIG. 3), the logic circuit 10 is activated once during each period T of the above-described M-sequence signal so that the gate circuit 11 is opened. Consequently, one bit of data is transmitted from an output circuit 12 to the data transmission bus line 3 at this time.
Similarly, each reception station or receiver 5 comprises a receiver circuit 13, shift registers 14, 15, and 16 and logic circuit 17. A gate 18 is opened only when a predetermined pattern is achieved during each period T of the above-described M-sequence signal so that a signal from the data transmission bus line 3 is received by an input circuit 19.
In this way, data transmission and reception are made possible between transmitters 4 and corresponding receivers 5 having logic circuits 10 and 17 which have the same logical condition.
Therefore, each pair of transmission and reception stations 4 and 5 can transfer data asynchronously with the remaining transmission and reception stations having different established conditions. Consequently, the transfer of data can be made without collision of data.
However, since only one bit of data can be transferred whenever each gate circuit 11 and 18 is opened in the conventional data transmission network system, the number of bits per frequency period of the above-described M-sequence signal must be increased. Therefore, the construction of the synchronous signal generator 1 becomes complicated and the number of stages of the shift registers in each station is increased accordingly, thus resulting in the increase of the cost and the reduction of processing speed.
In addition, the reliability of the network system is reduced since data transfer in units of one bit does not provide enough information to check for the occurrence of bit error.